PROGRAMMING THE INPUT / OUTPUT OF THE F68CH11 All of the F68HC11 onboard input/output features are controlled by a single register block of 64 locations. Understanding the use of those registers means understanding all the I/O features of the F68HC11. The location of this register block is controlled (you might have guessed) by a register. Upon reset this register establishes the register block at $1000. Although the Max-FORTH operating system allows modification, the register set will normally be moved by the operating system to $B000 for Rev 2 parts ($9000 for Rev 0 and Rev 1) to give the most consistantly contiguous memory map possible. (At $B000, the registers are in the same 4K block of memory already partitioned by the EEPROM.) The following discus- sion assumes the register set is a $B000. The number of register may seem formidable. It will be easier to understand them by first grouping them by their function. There are five major groups: port, timer, serial channel, A/D and mis- celaneous. The 68HC11 includes a 40 I/O pins in five 8-bit ports. All of these pins serve multiple functions depending on the operating mode and the internal control registers. These registers are in memory from $B000 to $B00A. PORTA $B000 PIOC $B002 PORTC $B003 PORTB $B004 PORTCL $B005 DDRC $B007 PORTD $B008 DDRD $B009 PORTE $B00A The first register, PORTA at $B000, is used to read and write Port A. When Port A is used for general purpose I/O bits, bits 0, 1 and 2 are configured for input-only and writes to these bits have no meaning or effect. Bits 3, 4, 5 and 6 of Port A are con- figured for output-only. Reads of these bits return the levels sensed at the inputs to the pin drivers. Port A bit 7 (PA7) can be configured as a general-purpose I/O using the DDRA7 bit in the PACTL register. Port A may also be configured as: three input capture functions (IC1, IC2, IC3), four output compare functions (OC2, OC3, OC4, OC5), with a pulse accumulator input (PA1) or a fifth output compare functions (OC1). Each port A that is not used for a capture or compare function may be used as a general purpose input or output line. 1 B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | PA7 | PA6 | PA5 | PA4 | PA3 | PA2 | PA1 | PA0 | $B000 PORTA |-----|-----|-----|-----|-----|-----|-----|-----| The second location at $B001 is reserved and has no function cur- rently. The Port I/O Control register, PIOC at location $B002, has a col- lection of control bits dealing largley with handshake control. With the except bit 7, which is read only, the PIOC is a read/write register. Due to the complexity of the bits in the PIOC each bit will be described separately. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | STAF| STAI| CWOM| HNDS| OIN | PLS | EGA | INVB| $B002 PIOC |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 STAF Strobe A Interrupt Status Flag. This bit is set when a selected edge of strobe A occurs. Clearing it depends on the state of HNDS and OIN bits. STAF is cleared by reset. |------|-----|------------------------------------------------------------| | HNDS | OIN | Clearing Mechanism | |------|-----|------------------------------------------------------------| | 0 | X | Reading PIOC (with STAF Set) Followed by a Read of PORTCL | | 1 | 0 | Reading PIOC (with STAF Set) Followed by a Read of PORTCL | | 1 | 1 | Reading PIOC (with STAF Set) Followed by a Write to PORTCL | |------|-----|------------------------------------------------------------| Bit 6 STAI Strobe A Interrupt Enable Mask. When this bit is set and the I bit in the condition code register is clear, STAF (when set) will request an interrupt. STAI is cleared by reset. Bit 5 CWOM Port C Wire-OR Mode. When clear, port C operates normally. When set, port C behaves as open-drain outputs. CWOM is cleared by reset. Bit 4 HNDS Handshake Mode. When clear, strobe A acts as a simple input strobe to latch data into PORTCL, and strobe B acts as a simple output strobe which pulses after a write to port B. When set a handshake protocol involving port C, STRA and STRB is selected (see the definition of the OIN bit). 2 Bit 3 OIN Output or Input Handshaking. This bit has no meaning when HNDS=0. Otherwise, when OIN is clear, input handshake mode is selected. When OIN is set, output handshake mode is selected. OIN is cleared by reset. Bit 2 PLS Pulse/Interlocked Handshake Operation. This bit has no meaning if HNDS=0. When PLS is clear, interlocked hand- shake operation is selected. In this mode, strobe B, once activated, stays active until the selected edge of strobe A is detected. When PLS is set, strobe B is pulsed for two E cycles. This bit is undefined coming out of reset. Bit 1 EGA Active Edge for Strobe A. When clear, falling edge of STRA is selected. When output handshake is selected, port C bits obey the DDRC while STRA is low, but port C is forced to output when STRA is high. When set, rising edge of STRA is selected. When output handshake is selected, port C bits obey the DDRC while STRA is high, but port C is forced to output when STRA is low. This bit is set by reset. Bit 0 INVB Invert strobe B. When clear, the active level on strobe B is a logic zero. When set, the active level on strobe B is a logic one. It is set by reset. Location $B004, PORTC, is the used to read and write the Port C pins. All Port C pins are general-purpose input/output pins. The direction of the Port C lines are controlled by a direction register, DDRC. Port C inputs can be latched by the STRA input. Port C may also be used in full handshake modes of parallel I/O where the STRA input and STRB output act as handshake control lines. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | PC7 | PC6 | PC5 | PC4 | PC3 | PC2 | PC1 | PC0 | $B003 PORTC |-----|-----|-----|-----|-----|-----|-----|-----| Location $B005, PORTB, is the used to read and write Port B. All of the port B pins are general-purpose output pins. During reads of this port, the level sensed at the input side of the port B output drivers is read. Port B may also be used in a simple strobed output mode where the STRB pulses each time port B is written. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | PB7 | PB6 | PB5 | PB4 | PB3 | PB2 | PB1 | PB0 | $B004 PORTB |-----|-----|-----|-----|-----|-----|-----|-----| 3 Location $B005, PORTCL, is the used to read Port C, but it returns the value latched at the time of the last significant edge on STRA. All Port C pins are general-purpose input/output pins. The direction of the Port C lines are controlled by a direction register, DDRC. Port C inputs can be latched by the STRA input. Port C may also be used in full handshake modes of parallel I/O where the STRA input and STRB output act as hand- shake control lines. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | PC7 | PC6 | PC5 | PC4 | PC3 | PC2 | PC1 | PC0 | $B005 PORTCL |-----|-----|-----|-----|-----|-----|-----|-----| The next location at $B006 is reserved and has no function cur- rently. A data direction register, DDRC at $B007, determines if in- dividual Port C pins are input or outputs. The data direction register itself can be read, or written to set the Port C I/O directions. Each bit in PORTC data register has a bit in the position the DDRC register. When a bit is configured for output by being set, the value returned by a read is the value at the input to the pin driver. When a line is configured as an input, by clearing the DDRC bit, the pin becomes a high impedance input. If a write is executed to a line that is configured as an input, the value does not affect the I/O pin, but the bit is stored in an internal latch so that if the line is later reconfigured as an output, then this value appears at the I/O pin. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit 7|Bit 6|Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0| $B007 DDRC |-----|-----|-----|-----|-----|-----|-----|-----| Location $B008, PORTD, is the used to read and write Port D. Port D bits 0-5 may be used for general I/O or with the serial communications interface (SCI) and serial pheripheral interface (SPI) subsystems. Bits 6 and 7 are used as handshake control sig- nals for ports B and C. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | | | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 | $B008 PORTD |-----|-----|-----|-----|-----|-----|-----|-----| 4 A data direction register, DDRD at $B009, determines if the five individual general purpose Port D pins act as input or outputs. The data direction register itself can be read, or written to set the Port D I/O directions. Each bit in PORTD data register has a bit in the position the DDRC register. When a bit is configured for output by being set, the value returned by a read is the value at the input to the pin driver. When a line is configured as an input, by clearing the DDRD bit, the pin becomes a high im- pedance input. If a write is executed to a line that is con- figured as an input, the value does not affect the I/O pin, but the bit is stored in an internal latch so that if the line is later reconfigured as an output, then this value appears at the I/O pin. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | | |Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0| $B009 DDRD |-----|-----|-----|-----|-----|-----|-----|-----| Note that bits 6 and 7 of Port D are dedicated to bus control (AS and R/W) while in expanded mode or parallel I/O strobes (STRA and STRB) while in single chip modes. For this reason, bits 6 and 7 of Port D are not available as general purpose I/O lines and the associated bits in the DDRD and PORTD registers are not imple- mented. Location $B00A, PORTE, is the used to read Port E. In all operat- ing modes, Port E is used for general-purpose inputs and/or analog-to-digital (A/D) channel inputs. Port E should not be read while an A/D conversion is actually taking place. Writes to the PORTE address have no meaning or effect. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | PE7 | PE6 | PE5 | PE4 | PE3 | PE2 | PE1 | PE0 | $B00E PORTE |-----|-----|-----|-----|-----|-----|-----|-----| The largest of the five groups of registers concern the timer functions. CFORC $B00B OC1M $B00C OC1D $B00D TCNT $B00E TIC1 $B010 TIC2 $B012 5 TIC3 $B014 TOC1 $B016 TOC2 $B018 TOC3 $B01A TOC4 $B01C TOC5 $B01E TCTL1 $B020 TCTL2 $B021 TMSK1 $B022 TFLG1 $B023 TMSK2 $B024 TFLG2 $B025 PACTL $B026 PACNT $B027 The timer has a single 16-bit free-running counter which is clocked by the output of a four-stage prescaler (divide by 1, 4, 8 or 16), which is in turn driven by the MCU E clock. Input func- tions are called input captures. These input captures record the count from the free-running counter in response to a detected edge on an input pin. Output functions, called output compares, can automatically affect output pins when there is a match be- tween a 16-bit output-compare register and the free-running counter. Additionally, one output compare can affect any or all of the five output pins (Bits 7-3) in Port A at once, as a result of a successful compare. This function allows control of mul- tiple I/O pins automatically with a single output compare. This timer system has a total of three input capture register and five output compare registers. The first register in the group deals with the output compare function. The write-only register, CFORC at $B00B, allows output compares to be forced by writing is done to CFORC with the as- sociated bit set for each output compare that is to be forced. The action taken as a result of a forced compare is the same as if there was a match between the OCx register and the free- running counter, except that the corresponding interrupt flag status bits are not set. Reads of this location have no meaning or effect and always return logic zeros ($00). Five of the bit positions in the CFORC register, bits 7 - 3, cor- respond to the five output compares. Bits 2, 1 and 0 of the CFORC register are not implemented. Note that the compare force function is not generally recommended for use with the output toggle function because a normal compare occuring immediately before or after the force may result in the undesirable opera- tion. 6 B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | FOC1| FOC2| FOC3| FOC4| FOC5| - | - | - | $B00B CFORC |-----|-----|-----|-----|-----|-----|-----|-----| FOC1-FOC5 Force Output Compare x Action 0 - has no meaning 1 - causes the action which is programmed for output compare except that the OCxF is not set. Bits 2-0 Not implemented. Read as a logic zeros. The next register, OC1M at $B00C, is used in conjunction with Out- put Compare 1 to specify the bits of port A which are to be af- fected as a result of a successful OC1 compare. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |OC1M7|OC1M6|OC1M5|OC1M4|OC1M3| - | - | - | $B00C OC1M |-----|-----|-----|-----|-----|-----|-----|-----| The bits of OC1M register correspond bit-for-bit with the output bits of Port A (bits 7 through 3 only). For each bit that is af- fected by the successful Output 1 Compare, the corresponding bit in OC1M should be set to one. Bits zero through two are not implemented and always read as zeros. This register is cleared by reset. The register immediately following, OC1D at $B00D, is also used in conjunction with Output Compare 1. It specifies the data which is to be stored to the affected bits of Port A as the result of a successful OC1 compare. Bits zero through two are not implemented and always read as zeros. This register is not affected by reset. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |OC1D7|OC1D6|OC1D5|OC1D4|OC1D3| - | - | - | $B00D OC1D |-----|-----|-----|-----|-----|-----|-----|-----| The bits of 0C1D correspond bit-for-bit with the bits of port A (bits 7 through 3 only). When a successful OC1 compare occurs, for each bit that is set in OC1M, the corresponding data bit in OC1D is stored in the corresponding bit of port A. 7 If there is a conflicting situation where an OC1 compare and another output compare function occur during the same E cycle with both attempting to alter the same port A bit, the OC1 action overrides. (Note that the pulse accumulator function shares bit 7 of port A. If the DDRA7 control bit in the PACTL register is set, then Port A bit 7 is configured as an output and OC1 can obtain access by setting OC1M bit 7. Further, if the PAEN control bit in the PACTL register is set, enabling the pulse accumulator, OC1 com- pares cause the pulse accumulator to take the appropriate action of the pulse counting or gating mode). The next two locations, TCNT at $B00E and $B00F, can be used to read the counter at any time without affecting its value because it is clocked and read during opposite half cycles of the MPU E clock. A counter read should first address the most significant byte. An MPU read of this address causes the least significant byte to be transferred to a buffer. This buffer is not affected by reset and is accessed when reading the least significant byte of the counter. For double byte read insructions, the two ac- cesses occur on consecutive bus cycles. The counter is cleared to $0000 during reset and is a read-only register in all but the test mode. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit15| - | - | - | - | - | - |Bit 8| $B00E \ |-----|-----|-----|-----|-----|-----|-----|-----| > TCNT |Bit 7| - | - | - | - | - | - |Bit 0| $B00F / |-----|-----|-----|-----|-----|-----|-----|-----| The input capture registers are 16-bit read-only registers which are not affected by reset and are used to latch the value of the counter when a defined transition is sensed by the corresponding input capture edge detector. (The level transition which trig- gers counter transfer is defined by the corresponding input edge bits, EDGxB and EDGxA, in TCTL2.) B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| 8 |Bit15| - | - | - | - | - | - |Bit 8| $B010 \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC1 |Bit 7| - | - | - | - | - | - |Bit 0| $B011 / |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit15| - | - | - | - | - | - |Bit 8| $B012 \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC2 |Bit 7| - | - | - | - | - | - |Bit 0| $B013 / |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit15| - | - | - | - | - | - |Bit 8| $B014 \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC3 |Bit 7| - | - | - | - | - | - |Bit 0| $B015 / |-----|-----|-----|-----|-----|-----|-----|-----| The result obtained by an input capture corresponds to the value of the counter one cycle after the transition which triggered the edge-detection logic. The selected edge transition sets the ICxF in TFLG1 and can cause an interrupt if the corresponding ICxI bit(s) is (are) set in the TMSK1 register. A read of the Input Capture Register's MSB inhibits captures for one E cycle to allow a double-byte read of the full 16-bit register. The output compare registers are 16-bit read/write registers which are initialized to $FFFF by reset. They can be used as out- put waveform controls and as elapsed time indicators. If an out- put compare is not utilized, the unused registers may be as storage locations. All output compare registers have a separate dedicated comparator for comparing against the free-running counter. If a match is found, the corresponding output compare flag (OCxF) bit in TFLG1 is set and a specified action is automatically taken. For output compare functions two through five, the automatic action is con- trolled by pairs of bits in the TCTL1 control register (OMx and OLx). Each pair of control bits are encoded to specify the out- put action taken as a result of a successful OCx compare. An interrupt can also accompany a successful output compare, provided that the corresponding interrupt enable bit (OCx1) is set in TMSK1. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| 9 |Bit15| - | - | - | - | - | - |Bit 8| $B016 \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC1 |Bit 7| - | - | - | - | - | - |Bit 0| $B017 / |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit15| - | - | - | - | - | - |Bit 8| $B018 \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC2 |Bit 7| - | - | - | - | - | - |Bit 0| $B019 / |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit15| - | - | - | - | - | - |Bit 8| $B01A \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC3 |Bit 7| - | - | - | - | - | - |Bit 0| $B01B / |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit15| - | - | - | - | - | - |Bit 8| $B01C \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC4 |Bit 7| - | - | - | - | - | - |Bit 0| $B01D / |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit15| - | - | - | - | - | - |Bit 8| $B01E \ |-----|-----|-----|-----|-----|-----|-----|-----| > TIC5 |Bit 7| - | - | - | - | - | - |Bit 0| $B01F / |-----|-----|-----|-----|-----|-----|-----|-----| After an MPU write cycle to the most significant byte, output com- pares are inhibited for one E cycle in orded to allow writing two consecutive bytes before making the next comparison. If both bytes of the register are to be changed, a double-byte write in- struction should be used in order to take advantage of the com- pare inhibit feature. MPU writes can be made to either byte of the output compare register without affecting the other byte. Timer Control Register 1, TCTL1, is an 8-bit read/write register. All bits in this register are cleared to zero during reset. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | OM2 | OL2 | OM3 | OL3 | OM4 | OL4 | OM5 | OL5 | $B020 TCTL1 |-----|-----|-----|-----|-----|-----|-----|-----| Bits 7, 5, 3, 1 - OMx Output Mode. Bits 6, 4, 2, 0 - OLx Output Level. 10 These two control bits (OMx and OLx) are encoded to specify the output action to be taken as a result of a successful OCx com- pare. OMx OLx Action Taken Upon Successful Compare 0 0 Timer disconnected from output pin logic 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one Timer Control Register 2, TCTL2, is an 8-bit read/write register except for bits 6 and 7 which are not implemented. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | - | - |EDG1B|EDG1A|EDG2B|EDG2A|EDG3B|EDG3A| $B021 TCTL2 |-----|-----|-----|-----|-----|-----|-----|-----| Bits 7, 6 Not implemented. Read as logic zeros. Bits 5, 3, 1 EDGxB Input Capture x Edge Control. These two bits (EDGxB and EDGxA) are cleared to zero by Bits 4, 2, 0 EDGxA reset and are encoded to configure the input sensing logic for input capture x as follows: EDGxB EDGxA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any (rising or falling) edge The timer interrupt mask register, TMSK1, is a read/write register. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | OC11| OC21| OC31| OC41| OC51| IC11| IC21| IC31| $B022 TMSK1 |-----|-----|-----|-----|-----|-----|-----|-----| Bits 7-3 OCxI Output Compare x Interrupt. If the OCxI mask bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested. 11 Bits 2-0 ICxI Input Capture x Interrupt. If the ICxI mask bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. The Timer System Flag Register 1, TFLG1, is used to indicate the occurence of timer system events and together with the TMSK1 register allows the timer sub-system to operate in a polled or interrupt driven system. For each bit in the timer flag register 1 (TFLG1), there is a corresponding bit in the timer mask register 1 (TMSK1) in the same bit position. If, and only if, the mask bit is set each time the conditions for the correspond- ing flag are met, a hardware interrupt sequence is requested as well as the flag bit being set. To clear a flag in this register a pattern of ones should be writ- ten to the bits to be cleared. The zeros in that pattern will not affect the state of any bit. Bit manipulation instructions would be inappropriate for flag clearing because they are read- modify-write instructions. Even though the instruction mask im- plies that the programmer is only interested in some of the bits in the manipulated location, the entire 8-bit location is ac- tually read and rewritten which may clear other bits in the register. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | OC1F| OC2F| OC3F| OC4F| OC5F| IC1F| IC2F| IC3F| $B023 TFLG1 |-----|-----|-----|-----|-----|-----|-----|-----| Bits 7-3 OCxF Output Compare x Flag. This flag bit is set each time the timer counter matches the output compare register x value. A write of zero does not affect the state of this bit. A write of a one causes this bit to be cleared. Bits 2-0 ICxF Input Capture x Flag. This flag bit is set each time a selected active edge is detected on the ICx input line. A write of a zero does not affect this bit. A write of a one causes this bit to be cleared. The Timer System Mask Register 2, TMSK2, is used to control wether or not a hardware interrupt sequence is requested as a result of a status bit being set in timer system flag register 2. In addition, two timer prescaler bits are included in this register. For each of the four most significant bits in timer flag register 2 (TFLG2), there is a corresponding bit in the timer mask register 2 (TMSK2) in the same bit position. All bits in the TMSK2 Register are cleared by reset. 12 B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | TOI | RTII|PAOVI| RAII| - | - | PR1 | PR0 | $B024 TMSK2 |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 TOI Timer Overflow Interrupt Enable. This read/write bit is cleared by reset. If this bit is set, a timer overflow interrupt request is initiated each time the TOF bit (in TFLG2) is set as a result of a timer counter overflow. Bit 6 RTI Interrupt Enable. This read/write bit is cleared to zero by reset and is used to enable or inhibit RTIF inter- rupt flags from causing hardware interrupt sequences. When RTII is clear, the RTIF flag is masked (inhibited). When RTII is set, the RTIF flag is enabled to cause a hardware interrupt. Bit 5 PAOVI Pulse Accumulator Overflow Interrupt Enable. This read/write bit is cleared to zero by reset and is used to enable or inhibit PAOVF interrupt flags from causing hardware interrupt sequences. When it is set, a hardware interrupt results when the PAOVF bit is set. Bit 4 PAII Pulse Accumulator Input Interrupt Enable. This read/write bit is cleared to zero by reset and is used to enable or inhibit PAIF interrupt flags from causing hardware interrupt sequences. When it is set, a hardware interrupt results if the PAIF bit is set. Bit 3-2 These bits are not implemented. Reads of these bits will always return a logic zero. Bit 1-0 PR1,PR0 Timer Prescaler Selects. These two bits may be read at any time but may only be written during initializa- tion. Reset clears these bits. Writes are disabled after the first write or after 64 E cycles out of reset. If the MCU is in special test or special bootstrap mode, then these two bits may be written any time. These two bits specify the timer prescaler divide factor. PR1 PR0 Divide-by-Factor 0 0 1 0 1 4 1 0 8 1 1 16 13 Timer System Flag Register 2, TFLG2, is used to indicate the oc- curence of timer system events and together with the TMSK2 register, allows the timer sub-systems to operate in a polled or interrupt driven system. For each bit in timer flag register 2 (TFLG2), there is a corresponding bit in timer mask register 2 (TMSK2) in the same bit position. If the mask bit is set each time the conditions for the corresponding flag are met, a hardware interrupt sequence is requested, as well as the flag bit being set. The timer system status register indicates when interrupt condi- tions have occurred. To clear a bit or bits, a logic one is writ- ten to it, or them. Bit manipulation instructions would be inappropriate for flag clearing because they are read-modify-write instructions. Even though the instruction mask implies that the programmer is only interested in some of the bits in the manipulated location, the entire 8-bit location is actually read and rewritten which may clear other bits in the register. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | TOF | RTIF|PAOVF| PAIF| - | - | - | - | $B025 TFLG2 |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 TOF Timer Overflow. This bit is cleared by reset. It is set to one each time the 16-bit free-running counter ad- vances from a value of $FFFF to $0000. In order to acknow- ledge (clear) the TOF flag the user must perform a write operation to TFLG2 with bit 7 set. Bit 6 RTIF Real Time Interrupt Flag. This bit is cleared by reset. RTIF is set at each rising edge of the selected tap point. To clear the RTIF flag, a software write is per- formed to the TFLG2 register with bit 6 set to one. Bit 5 PAOVF Pulse Accumulator Overflow Interrupt Flag. This bit is cleared by reset and becomes set when the count in the pulse accumulator rolls over from $FF to $00. This bit is cleared by a write to the TFLG2 register with bit 5 set. Bit 4 PAIF Pulse Accumulator Input Edge Interrupt Flag. This bit is cleared by reset and becomes set when an active edge is detected on the PAI input pin. This bit is cleared by a write to the TFLG2 register with bit 4 set. Bits 3-0 These bits are not implemented and they read as logic zeros. 14 When the count changes from $FFFF to $0000, the timer overflow flag (TOF) bit is set in TFGL2. An interrupt can be enabled by setting the interrupt enable bit (TOI) in TMSK2. The real time feature on the 68HC11 is configured and controlled by two bits in the PACTL control register (RTR1 and RTR0) to select one of four interrupt rates. The RTII bit in TMSK2 enables the interrupt capability. Every timeout causes the RTIF bit to be set in TFLG2 and if RTII is set, an interrupt request is generated. After reset, one entire real time interrupt period elapses before the RTIF flag is set for the first time. The pulse accumulator is an 8-bit counter which can operate in etiher of two modes depending on the state of the PAMOD control bit in PACTL. In the event, counting mode, the 8-bit counter is clocked to increasing values by an external pin. In the gated time accumulation mode, an E/64 clock drives the 8-bit counter, but only while the external PAI input pin is in a selected state. The pulse accumulator uses port A bit 7 as its PAI input, but this pin also shares function as a general purpose I/O pin and as a timer output compare 1 output. Although the port A bit 7 would normally be configured as an input when being used for the pulse accumulator, it still drives the pulse accumulator system even when it is configured for use in its alternate capacities. Four bits in this register are used to control an 8-bit pulse ac- cumulator system and two other bits are used to select the rate for the real time interrupt system. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |DDRA7| PAEN|PAMOD|PEDGE| - | - | RTR1| RTR0| $B026 PACTL |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 DDRA7 Data Direction for Port A Bit 7. This read/write bit is cleared by reset and is used to enable or disable the output driver for the Port A bit 7 pin. When DDRA7 is zero, the Port A bit 7 pin is configured for input only and when DDRA7 is one, Port A bit 7 is configured for output. Note that even when Port A bit 7 is configured for output, this pin still acts as the input to the pulse accumulator system. Bit 6 PAEN Pulse Accumulator System Enable. This read/write bit is cleared by reset and is used to enable or disable the pulse accumulator system. When it is set, the pulse ac- cumulator is enabled, and when clear, the pulse accumulator system is disabled. 15 Bit 5 PAMOD Pulse Accumulator Mode. This read/write bit con- trols whether the pulse accumulator is to operate in the ex- ternal event counting mode or the gated time accumulation mode. When it is zero, the pulse accumulator counts pulses on the PAI input pin (port A bit 7). When it is set, the pulse accumulator operates in the gated time accumulation mode and the PAI input allows the pulse accumulator counter to count. The PAMOD bit is cleared to zero by reset. PAMOD PEDGE Action on Clock 0 0 PAI Falling Edge Increments the Counter 0 1 PAI Rising Edge Increments the Counter 1 0 A '0' on PAI Inhibits Counting 1 1 A '1' on PAI Inhibits Counting Bit 4 PEDGE Pulse Accumulator Edge Control. This read/write bit has different meanings depending on the state of the PAMOD control bit. This bit is cleared by reset. Bit 3-2 These bits are not implemented and read as logic zeros. Bit 1-0 RTR1,RTR0 RTI Interrupt Rate Selects. These two read/write bits select one of four rates for the real time period interrupt circuit. Reset clears these two bits and after reset, a full RTI periods elapses before the first RTI interrupt. |----------------------------------------------------------| | R R | | Xtal = | Xtal = | Xtal = | | T T | | 223 | 8.0 Mhz | 4.0 Mhz | | R R |Divide | | | | | 1 0 | E by | | | | |----------------------------------------------------------| | 0 0 | 213 | 3.91 ms | 4.10 ms | 8.19 ms | | 0 1 | 214 | 7.81 ms | 8.19 ms | 16.38 ms | | 1 0 | 215 | 15.62 ms | 16.38 ms | 32.77 ms | | 1 1 | 216 | 31.25 ms | 32.77 ms | 65.54 ms | |----------------------------------------------------------| | E = | 2.1 Mhz | 2.0 Mhz | 1.0 Mhz | |----------------------------------------------------| SPCR $B028 SPSR $B029 SPDR $B02A BAUD $B02B SCCR1 $B02C SCCR2 $B02D SCSR $B02E SCDR $B02F 16 The serial peripheral interface (SPI) is a synchronous interface built into the 68HC11 MCU which allows several several 68HC11 MCUs or a 68HC11 plus peripheral devices, to be interconnected. In an SPI, separate wires (signals) are required for data and clock as the clock is not included in the data stream. An SPI system may be configured as a master or as a slave. The four basic signals (MISO, MOSI, SCK and SS) used to transmit data by the serial peripheral interface are discussed in the fol- lowing paragraphs. Each signal is described for both the master and slave modes. Any SPI outputs has to have its corresponding data direction bit in DDRD set. If this bit is clear, the pin is disconnected from the SPI logic and becomes a general-purpose input. There are three registers in the serial peripheral interface which provide control, status and data strorage functions. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | SPIE| SPE | DWOM| MSTR| CPOL| CPHA| SPR1| SPR0| $B028 SPCR |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 SPIE When the serial peripheral interrupt enable bit is set, SPI interrupts are allowed. Interrupts are masked when this bit is cleared. The SPIE bit is cleared by reset. Bit 6 SPE When serial peripheral enable bit is set, it enables the SPI system by connecting it to the external pins. Be- cause the SPE bit is cleared by reset, the SPI system is not connected to the external pins upon reset. Bit 5 DWOM If the DWOM bit is set, Port D output pins function as open-drain outputs, and when the DWOM is clear, Port D output pins function normally. The DWOM bit is cleared by reset. Bit 4 MSTR If the MSTR bit is set, the SPI is a master device. If cleared, the SPI is a slave device. Bit 3 CPOL When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slabe. The CPOL bit is cleared by reset. 17 Bit 2 CPHA The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. In general, the CPHA bit selects which clock edge captures data and allows it to change states. The CPHA bit is set by reset. Bit 1-0 SPR1 SPR0 These two serial peripheral rate bits select one of four baud rates to be used as a SCK if a device is a master; however, they have no effect in the slave mode. The SPR1 and SPR0 bits are not affected by reset. |------|------|--------------------| | | | Internal Processor | | SPR1 | SPR0 | Clock Divide By | |------|------|--------------------| | 0 | 0 | 2 | | 0 | 1 | 4 | | 1 | 0 | 16 | | 1 | 1 | 32 | |------|------|--------------------| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | SPIF| WCOL| - | MODF| - | - | - | - | $B029 SPSR |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 SPIF The serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. If SPIF goes high and if SPIF is set, a serial peripheral interrupt is generated. While SPIF is set, all writes to the serial peripheral data register are inhibited. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an access of the SPDR. The SPIF bit is cleared by reset. Bit 6 WCOL The write collision bit is set when an attempt is made to write to the serial peripheraldata register while data transfer is taking place. Clearing the WCOL bit is ac- complished by reading th SPSR (with WCOL set) followed by an access to SPDR. The WCOL bit is cleared by reset. Bit 5 Not implemented and reads as zero. 18 Bit 4 MODF The mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default sys- tem state. The MODF bit is normally clear, and is set only when the master device has its SS pin pulled low. Setting the MODF bit affects the internal serial peripheral inter- face system in the following ways: 1. An SPI interrupt is generated if SPIE = 1 2. The SPE bit is cleared. This disables the SPI. 3. The MSTR bit is cleared, thus forcing the device into the slave mode. Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by awrite to the SPCR. Control bits SPE and MSTR maybe restored to their original set state after the MODF bit has been cleared. The MODF bit is cleared by reset. Bit 3-0 These bits are not implemented and read as zeros. 7 6 5 4 3 2 1 0 |--------------------------------------------------| | SERIAL PERIPHERAL DATA I/O REGISTER | $B02A SPDR |--------------------------------------------------| The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte and this will only occur in the master device. At the completion of trans- mitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist. A write to the serial peripheral data I/O register is not buf- fered and places data directly into the shift register for trans- mission. A full-duplex asynchronous Serial Communications Interface (SCI) is provided with a standard NRZ format (one start bit, eight or nine data bits and one stop bit) and a variety of baud rates. The SCI transmitter and receiver are functionally independent, but use the same data format and bit rate. "Baud" and "bit rate" are used synonymously in the following description. 19 Receive data (RxD) or transmit data (TxD) is the serial data which is transfered to the internal data bus from the input pin (RxD) and from the internal bus to the output pin (TxD). The user has option bits in serial communications control register 1 (SCCR1) to determine the "wake-up" method (WAKE bit) and data word length (M bit) of the SCI. Serial communications control register 2 (SCCR2) provides control bits which in- dividually enable/disable the transmitter or receiver (TE and RE, respectively) enable system interrupts (TIE, TCIE, ILIE) and provide the wake-up enable bit (RWU) and the send break code bit (SBK). The baud rate register bits allow the user to select dif- ferent baud rates which may be used as the rate control for the transmitter and receiver. Data transmission is initiated by a write to serial communica- tions data register (SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit serial shift register. This transfer of data sets the TDRE bit of the SCI status register (SCSR) and may generate an interrupt if the transmit interrupt is enabled. The transfer of data to the trans- mit shift register is synchronized with the bit rate clock. All data is transmitted bit zero first. Upon completion of data transmission, the TC (transmission complete) bit of the SCSR is set (provided no pending data, preamble or break is to be sent) and an interrupt may be generated if the transmit complete inter- rupt is enabled. If the transmitter is disabled and the data, preamble or break (in the transmit shift register) has been sent, the TC bit will also be set. This will also generate an inter- rupt is the TCIE bit is set. When the SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The RDRF bit of the SCSR is set to indicate that a data byte has been transfered from the input serial shift register to the SCDR, which can cause an inter- rupt if the receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error bits of the SCSR may be set if data recep- tion errors occured. An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle line transmission) of SCSR is set. This allows a receiver that is not in the wake- up mode to detect the end of a message, the preamble of a new mes- sage or to resynchronize with the transmitter. The baud rate register, BAUD, provides the means for selecting different baud rates which may be used as the rate control for the transmitter and receiver. The SCP0-SCP1 bits function as a prescaler for the SCR0-SCR2 bits. Together, these five bits provide multiple baud rate combinations for a given crystal fre- quency. 20 B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | - | - | SCP1| SCP0| - | SCR2| SCR1| SCR0| $B02B BAUD |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7-6 These two bits are not implemented. Bit 5 SCP1,SCP0 Table below shows the prescale values attained from the E clock. Reset clears SCP1-SCP0 bits (divide-by- one). |------|------|--------------------| | | | Internal Processor | | SCP1 | SCP0 | Clock Divide By | |------|------|--------------------| | 0 | 0 | 1 | | 0 | 1 | 3 | | 1 | 0 | 4 | | 1 | 1 | 13 | |------|------|--------------------| Bit 3 Not implemented. Bit 2-0 SCR2 SCR1 SCR0 These three bits select the baud rate of both the transmitter and the receiver. Table below shows the prescaler value that divides the output of the first stage. Reset does not affect the SCR2-SCR0. |------|------|------|------------------| | | | | Prescaler Output | | SCR2 | SCR1 | SCR0 | Divide By | |------|------|------|------------------| | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 2 | | 0 | 1 | 0 | 4 | | 0 | 1 | 1 | 8 | | 1 | 0 | 0 | 16 | | 1 | 0 | 1 | 32 | | 1 | 1 | 0 | 64 | | 1 | 1 | 1 | 128 | |------|------|------|------------------| 21 Note that there is a fixed rate divide-by-16 between the receive clock (RT) and the transmit clock (Tx). The actual divider chain is controlled by the combined SCP0-SCP1 and SCR0-SCR2 bits in the baud rate register as illustrated. |-----|----|-------------------------------------------------------------------| | SCP |CLK*| | | Bit | Dvd| Crystal Frequency (MHz) | |-----| By |-------------|-------------|------------|-------------|------------| | 0 1 | | 8.3886 | 8.0 | 4.9152 | 4.0 | 3.6864 | |-----|----|-------------|-------------|------------|-------------|------------| | 0 0 | 1 |131.072 KBaud|125.000 KBaud| 76.80 KBaud| 62.50 KBaud| 57.60 KBaud| | 0 1 | 3 | 43.690 KBaud| 41.666 KBaud| 25.60 KBaud| 20.833 KBaud| 19.20 KBaud| | 1 0 | 4 | 32.768 KBaud| 31.250 KBaud| 19.20 KBaud| 15.625 KBaud| 14.40 KBaud| | 1 1 | 13 | 10.082 KBaud| 9600 Baud| 5.907 KBaud| 4800 Baud| 4430 Baud| |-----|----|-------------|-------------|------------|-------------|------------| * The clock in the "Clock Divided By" column is in theinternal processor clock. Note: The divided frequencies shown above represent baud rates which are the highest transmit baud rate (Tx) that can be ob- tained by a specific crystal frequency and only using the pres- caler division. Lower baud rates may be obtained by providing a further division using the SCI rate select bits as shown on Table for some representative prescaler outputs. |-------|-------|------------------------------------------------------------| | SCP | | | | Bit | CLK* | Crystal Frequency (MHz) | |-------|Divided|-------------|------------|-----------|-----------|---------| | 2 1 0 | By |131.072 KBaud|32.768 KBaud|76.80 KBaud|19.20 KBaud|9600 Baud| |-------|-------|-------------|------------|-----------|-----------|---------| | 0 0 0 | 1 |131.072 KBaud|32.768 KBaud|76.80 KBaud|19.20 KBaud|9600 Baud| | 0 0 1 | 2 | 65.536 KBaud|16.384 KBaud|38.40 KBaud| 9600 Baud|4800 Baud| | 0 1 0 | 4 | 32.768 KBaud| 8.192 KBaud|19.20 KBaud| 4800 Baud|2400 Baud| | 0 1 1 | 8 | 16.384 KBaud| 4.096 KBaud| 9600 Baud| 2400 Baud|1200 Baud| | 1 0 0 | 16 | 8.191 Kbaud| 2.048 KBaud| 4800 Baud| 1200 Baud| 600 Baud| | 1 0 1 | 32 | 4.096 KBaud| 1.024 KBaud| 2400 Baud| 600 Baud| 300 Baud| | 1 1 0 | 64 | 2.048 KBaud| 512 Baud| 1200 Baud| 300 Baud| 150 Baud| | 1 1 1 | 128 | 1.024 KBaud| 256 Baud| 900 Baud| 150 Baud| 75 Baud| |-------|-------|-------------|------------|-----------|-----------|---------| Note: This illustrates how the SCI select bits can be used to provide lower transmitter baud rates by further dividing the pres- caler output frequency. The five examples are only representa- tive samples. In all cases, the baud rates shown are transmit baud rates (transmit clock) and the receiver clock is 16 times higher in frequency than the actual baud rate. The Serial Communications Control Register 1, SCCR1, provides the control bits which: 22 1. determine the word length and 2. selects the method used for the wake-up feature B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | R8 | T8 | - | M | WAKE| - | - | - | $B02C SCCR1 |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 R8 If the M bit is set, then this bit provides a storage location for the ninth bit in the receive data word. Reset does not affect this bit. Bit 6 T8 If the M bit is set, then this bit provides a storage location for the ninth bit in the transmit data word. Reset does not affect this bit. Bit 5 This bit is not implemented and reads as zero Bit 4 M This bit selects the word length. Reset clears this bit. 0 = 1 start bit, 8 data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1 stop bit Bit 3 WAKE This bit allows the user to select the method for receiver "wake-up". When clear, an idle line condition (10 consecutive ones if M=0 or 11 consecutive ones if M=1) will wake-up the receiver. When set, detection of a one in last data bit (eight data bit if M=0, ninth data bit if M=1) will wake-up the receiver. Bit 2-0 These bits are not implemented and read as zeros. The serial communications control register 2, SCCR2, provides con- trol bits which individually enable/disable the SCI functions. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | TIE | TCIE| RIE | ILIE| TE | RE | RWU | SBK | $B02D SCCR2 |-----|-----|-----|-----|-----|-----|-----|-----| 23 Bit 7 TIE When the transmit interrupt enable bit is set, the SCI interrupt occurs when TDRE is set. When TIE is clear, the TDRE interrupt is disabled. Cleared by reset. Bit 6 TCIE When the transmission complete interrupt enable bit is set, the SCI interrupt occurs when TC is set. When TCIE is clear, the TC interrupt is disabled. Cleared by reset. Bit 5 RIE When the receive interrupt enable bit is set, the SCI interrupt occurs when OR or RDRF are set. When RIE is clear, the OR and RDRF interrupts are disabled. Cleared by reset. Bit 4 ILIE When the idle line interrupt enable bit is set, the SCI interrupt occurs when IDLE is set. When ILIE is clear, the IDLE interrupt is disabled. Cleared by reset. Bit 3 TE When the transmit enable bit is set, the transmit shift register output is applied to the TxD line. Depending on the state of control bit M (SCCR), a preamble of 10 (M=0) or 11 (M=1) consecutive ones is transmitted when software sets the TE bit from a cleared state. After loading the last byte in the serial communications data register and receiv- ing the interrupt from TDRE, the user can clear TE. Trans- mission of the last byte will then be completed before the transmitter gives up control of the TxD pin. Cleared by reset. Bit 2 RE When the receive enable bit is set, the receiver is enabled. When RE is clear, the receiver is disabled and all of the status bits associated with the receiver (RDRF, IDLE, OR, NF and FE) are inhibited. Cleared by reset. Bit 1 RWU When the receiver wake-up bit is set, it enables the "wake-up" function. If the WAKE bit is cleared, RWU is cleared after receiving 10 (M=0) or 11 (M=1) consecutive ones. If the WAKE bit is set, RWU is cleared after receiv- ing a data word whose MSB is set. Cleared by reset. Bit 0 SBK If the send break bit is toggled set and cleared, the transmitter sends 10 (M=0) or 11 (M=1) zeros and then reverts to idle or sending data. If SBK remains set, the transmitter will continually send whole blocks (sets of 10 or 11) zeros until cleared. At the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. Reset clears the SBK bit. The serial communications status register, SCSR, provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. 24 B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | TDRE| TC | RDRF| IDLE| OR | NF | FE | - | $B02E SCSR |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 TDRE The transmit data register empty bit is set to indi- cate that the content of of the serial communications data register have been transferred to the transmit serial shift register. This bit is cleared by reading the SCSR (with TDRE=1) followed by a write to the SCDR. Reset sets the TDRE bit. Bit 6 TC The transmit complete bit is set at the end of a data frame, preamble, or break condition if: 1. TE= 1, TDRE = 1 and no pending data, preamble or break is to be transmitted; or 2. TE = 0 and the data, preamble, or break (in the transmit shift register) has been transmitted. The TC bit is a status flag which indicates that one of the above conditions have occured. The TC bit is cleared by reading the SCSR (with TC set) followed by a write to the SCDR. Reset sets the TC bit. Bit 5 RDRF The receive data register full bit is set when the receiver serial shift register is transferred to the SCDR. The RDRF bit is cleared when the SCSR is read (with RDRF set) followed by a read of the SCDR. Reset clears the RDRF bit. Bit 4 IDLE The idle line detect bit, when set, indicates a receiver idle line is selected. The IDLE bit is cleared by reading the SCSR with IDLE set followed by a read of the SCDR. The IDLE bit is inhibited when the RWU bit is set. Reset clears the IDLE bit. Bit 3 OR The overrun bit is set when the next byte is ready to be transferred from the receive shift register to the SCDR which is already full (RDRF bit is set). The only valid data is located in SCDR when OR is set. The OR bit is cleared when the SCSR is read (with OR set), followed by a read of the SCDR. Reset clears the OR bit. 25 Bit 2 NF The noise flag bit is set if there is noise on any of the received bits, including the start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is read (with NF set), followed by a read of the SCDR. Reset clears the NF bit. Bit 1 FE The framing error bit is set when no stop bit was detected in the data string received. The FE bit is set at the same time as the RDRF is set. If the byte received causes both framing and overrun errors, the processor will only recognize the overrun error. The framing error flag inhibits further transfer of data into SCDR until it is cleared. The FE bit is cleared when the SCSR is read (with FE=1) followed by a read of the SCDR. Reset clears the FE bit. Bit 0 Not implemented. Reads as zero. The serial communications data register, SCDR, performs two func- tions, i.e., it acts as the receive data register when it is read and as the transmit data register when it is written. B7 B6 B5 B4 B3 B2 B1 B0 |------------------------------------------------| | SERIAL COMMUNICATIONS DATA REGISTER | $B02F SCDR |------------------------------------------------| ADCTL $B030 ADR1 $B031 ADR2 $B032 ADR3 $B033 ADR4 $B034 The 68HC11 includes an 8-channel multiplexed-input successive ap- proximation analog-to-digital (A/D) converter with sample and hold to minimize conversion errors caused by rapidly changing in- put signals. Two dedicated pins (VRL, VRH) are provided for the reference supply voltage inputs. These pins may be connected to a lower noise power supply to assure full accuracy of the A/D con- version. The 8-bit A/D converter has a linearity error of 1/2 LSB and accepts analog inputs which range from VRL to VRH. Smaller analog input ranges can also be obtained by adjusting VRH and VRL to the desired upper and lower limits. Each conversion is accomplished in 32 MCU E clock cycles, provided the E rate is equal to or greater than 1 MHz. For systems which operate at 26 clock rates less than 1.0 MHz, an internal R-C oscillator must be used to clock the A/D system by setting the CSEL bit in the OP- TION register. All bits in the ADCTL register may be read or written, except bit 7 which is a read-only status indicator and bit 6 which always reads as zero. Bit 7 is cleared at reset but the other bits are not affected by reset. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | CCF | - | SCAN| MULT| CD | CC | CB | CA | $B030 ADCTL |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 CCF Conversion Complete Flag. This read-only status in- dicator is set when all four A/D result registers contain valid conversion results. Each time the ADCTL register is written, this bit is automatically cleared to zero and a con- version sequence is started. In the continuous modes, con- versions continue in a round-robin fashion and the result registers continue to be updated with current data even though the CCF bit remains set. Note: The user must write to register ADCTL to initiate con- version. Bit 6 Not implemented. Reads as zero. Bit 5 SCAN Continuous Scan Control. When this control bit is cleared, the four requested conversions are performed once to fill the four result registers. When this control bit is set, conversions continue in a round-robin fashion with the result registers being updated as data becomes available. Bit 4 MULT Multi-Channel/Single Channel Control. When this bit is cleared, the A/D system is configured to perform four con- secutive conversions on the single channel specified by the four channel select bits CD through CA (bits 3-0 of ADCTL). When this bit is set, the A/D system is configured to per- form a conversion on each of four channels where each result register corresponds to one channel. Bit 3-0 CD CC CB CA Channel Select D, Channel Select C, Channel Select B, Channel Select A. Bits 3 through 0 are used to select one of 16 A/D channels. When a multiple channel mode is selected (MULT = 1), the two least-significant select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four channels to be converted. The signals selected by the four channel select control bits are shown in the table below. 27 |----|----|----|----|----------------|----------------| | | | | | | Result in ADRx | | CD | CC | CB | CA | Channel Signal | if MULT=1 | |----|----|----|----|----------------|----------------| | 0 | 0 | 0 | 0 | AN0 | ADR1 | | 0 | 0 | 0 | 1 | AN1 | ADR2 | | 0 | 0 | 1 | 0 | AN2 | ADR3 | | 0 | 0 | 1 | 1 | AN3 | ADR4 | |----|----|----|----|----------------|----------------| | 0 | 1 | 0 | 0 | AN4* | ADR1 | | 0 | 1 | 0 | 1 | AN5* | ADR2 | | 0 | 1 | 1 | 0 | AN6* | ADR3 | | 0 | 1 | 1 | 1 | AN7* | ADR4 | |----|----|----|----|----------------|----------------| | 1 | 0 | 0 | 0 | RESERVED | ADR1 | | 1 | 0 | 0 | 1 | RESERVED | ADR2 | | 1 | 0 | 1 | 0 | RESERVED | ADR3 | | 1 | 0 | 1 | 1 | RESERVED | ADR4 | |----|----|----|----|----------------|----------------| | 1 | 1 | 0 | 0 | VRH Pin | ADR1 | | 1 | 1 | 0 | 1 | VRL Pin | ADR2 | | 1 | 1 | 1 | 0 | (VRH)/2 | ADR3 | | 1 | 1 | 1 | 1 | RESERVED | ADR4 | |----|----|----|----|----------------|----------------| There are two variations of single-channel operation. In the first variation (SCAN=0), the single-selected channel is con- verted four consecutive times with the first result being stored in the ADR4 register/ After the fourth conversion is complete, all conversion activity is halted until a new conversion command is written to the ADCTL control register. In the second varia- tion (SCAN=1), conversions continue to be performed on the selected channel with the fifth conversion being stored to the ADR1 register (overwriting the first conversion result), the sixth conversion overwrites ADR2, and so on continuously. There are two variations in multiple-channel operation. In the first variation (SCAN=0), the selected group of four channels are converted, one each each, with the first result being stored in the ADR1 result register and the fourth result being stored to the ADR4 register. After the fourth conversion is complete, all conversion activity is halted until a new conversion command is written to the ADCTL control register. In the second variation (SCAN=1), conversions continue to be performed on the selected group of channels with the fifth conversion being stored in the ADR1 register (replacing the earlier conversion result for the first channel in the group), the sixth conversion overwrites ADR2, and so on continuously. 28 The A/D result registers are read-only registers used to hold an 8-bit conversion result. Writes to these registers have no ef- fect. Data in the A/D result registers is not valid unless the CCF flag bit in ADTCL is set, indicating conversion complete. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit 7| - | - | - | - | - | - |Bit 0| $B031 ADR1 |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit 7| - | - | - | - | - | - |Bit 0| $B032 ADR2 |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit 7| - | - | - | - | - | - |Bit 0| $B033 ADR3 |-----|-----|-----|-----|-----|-----|-----|-----| B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit 7| - | - | - | - | - | - |Bit 0| $B034 ADR4 |-----|-----|-----|-----|-----|-----|-----|-----| The next four locations at $B035 through $B038 are reserved and have no function currently. OPTION $B039 COPRST $B03A PPROG $B03B HPRIO $B03C INIT $B03D TEST1 $B03E CONFIG $B03F The Configuration Options Register (OPTION) is a special purpose 8-bit register that is used (optionally) during initialization to configure internal system configuration options. With the excep- tion of bits 7, 6 and 3 (ADPU, CSEL and CME) which may be read or written at any time, this register may be written to only once after a reset and thereafter is a read-only register. If no write is performed to this location within 64 E-clock cycles after reset, then bits 5, 4, 1 and 0 (IRQ, DLY, CR1 and CR0) will become read-only to minimize the possibility of any accidental changes to the system configuration. While in special test modes, the protection mechanism on this register is overridden and all bits in the OPTION register may be written. 29 B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | ADPU| CSEL| IRQE| DLY | CME | - | CR1 | CR0 | $B039 OPTION |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 ADPU A/D Powerup. This bit is cleared by reset and con- trols operation of the on-chip analog-to-digital converter. When ADPU is clear, the A/D system is powered down and con- version requests will not return meaningful information. To use the A/D system, this bit should be set. Bit 6 CSEL A/D Clock Source Select. This bit is cleared by reset and determines the clocking source for the on-chip A/D. When this bit is zero, the MCU E clock drives the A/D system. When CSEL is one, an on-chip R-C oscillator is enabled and clocks the A/D system at about 1.5 MHz rate. When running with an E clock less than 1 MHz, CSEL must be high to program or erase the EEPROM. Bit 5 IRQE IRQ Edge/Level Sensitive. This read/write bit is cleared at reset. When it is clear, the IRQ pin is con- figured for level sensitive wired-OR operation (low level) and when it is set, the IRQ is configured for edge-only sen- sitivity (falling edges) on the IRQ pin. Bit 4 DLY STOP Exit Turn-On Delay. This bit may only be writ- ten under special circumstances as described above. This bit is set to one during reset and controls whether or not a relatively long turn-on delay will be imposed before process- ing can resume after a STOP period. If an external clock source is supplied this delay can be inhibited so that processing can resume within a few cycles of a wake up from STOP mode. When DLY is a one, delay is imposed to allow os- cillator stabilization and when DLY is a zero, this delay is bypassed. Bit 3 CME Clock Monitor Enable. This control bit may be read or written at any time and controls whether or not the internal clock monitor circuit will trigger a reset sequence when a slow or absent system clock is detected. When it is clear, the clock monitor circuit is disabled and when it is set, the clock monitor circuit is enabled. Systems operating at or below 200 KHz should not use the clock monitor function. Reset clears the CME bit. Bit 2 Not implemented and reads as a logic zero. Bit 1-0 CR1-CR0 COP Timer Rate Selects. |----------------------------------------------------------| | | | Xtal = | Xtal = | Xtal = | 30 | C C | E/215 | 223 | 8.0 Mhz | 4.0 Mhz | | R R |Dvd'ed | Timeout | Timeout | Timeout | | 1 0 | by | -0/ +15.6 ms | -0/ +15.6 ms | -0/ +15.6 ms | |----------------------------------------------------------| | 0 0 | 1 | 15.625 ms | 16.384 ms | 32.768 ms | | 0 1 | 4 | 62.5 ms | 65.536 ms | 131.07 ms | | 1 0 | 8 | 250 ms | 262.14 ms | 524.29 ms | | 1 1 | 16 | 1 s | 1.049 s | 2.1 s | |----------------------------------------------------------| | E = | 2.1 Mhz | 2.0 Mhz | 1.0 Mhz | |----------------------------------------------------| The clock monitor function is enabled by the CME control bit in the OPTION register. When CME is zero, the function is disabled and when CME is a one, the clock monitor function detects the ab- sence of an E clock for more than a certain period of time. The timeout period is dependent on processing parameters and will be between 5 and 100 microseconds. This means that an E-clock rate of 200 KHz or more will never cause a clock monitor failure and an E-clock rate of 10 KHz or less will definitely cause a clock monitor failure. This implies that systems operating near or below an E-clock rate of 200 KHz should not use the clock monitor function. Upon detection of a slow or absent clock, the clock monitor cir- cuit (if enabled by CME=1) will cause a system reset to be gener- ated. This reset is issued to the external system via the bidirectional RESET pin. Special considerations are needed when using a STOP function and clock monitor in the same system. Since the STOP function causes the clocks to be halted, the clock monitor function will generate a reset sequence if it is enabled at the time the STOP mode is entered. The 68HC11 includes 512 bytes of EEPROM located in the area $B600 through $B7FF which has the same read cycle time as the internal ROM. PPROG Register (EEPROM Programming Control) register is used to control programming and erasure of the 512-byte internal EEPROM. Reset clears this register to $00 so EEPROM is con- figured so EEPROM is configured for normal reads. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | ODD | EVEN| - | BYTE| ROW |ERASE|EELAT|EEPGM| $B03B |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 ODD Used to Program Odd Rows (TEST) 31 Bit 6 EVEN Used to Program Even Rows (TEST) Bit 5 - Not Implemented Bit 4 BYTE Used for Erasing Bytes - Overrides Bit 3 0 = Row or Bulk Erase 1 = Erase Only One Byte Bit 3 ROW Used for Row Erasing 0 = Bulk Erase 1 = Row Erase Bit 2 ERASE Enables the Erase 0 = Normal Read or Program 1 = Erase Mode Bit 1 EELAT EEPROM Latch Control 0=EEPROM Address and Data configured for Read 1=EEPROM Address and Data configured for Programming Bit 0 EEPGM Program Command 0 = Switched Off 1 = Turned On The operating modes for the 512-byte EEPROM are as follows: NORMAL READ - In this mode, the ERASE bit in the PPROG register must be clear (not programming mode). While these two bits are cleared, the ROW and EEPGM bits in the OPTION register have no meaning or effect, and the 512-byte EEPROM may be read as if it were a normal ROM. PROGRAMMING - During EEPROM programming, the ROW bit is not used. If the E clock frequency is less than 1 MHz the CSEL bit in the OPTION register must be set. Normal sequence of events in programming the EEPROM : 1) Write xxxx x010 to the PPROG register. This specifies program normal mode (ERASE bit=0), address/data buses con- figured to latch address and data information (EELAT bit=1), and erase voltage turned off (EEPGM bit=0). 2) Write data to be programmed to the desired EEPROM ad- dress. This write causes the address and data to be latched in a parallel internal latch. 3) Write EEPGM bit to one (xxxx x011). This couples the EEPROM programming supply voltage to the EEPROM array, to program the specified data into the specified data address in EEPROM. 32 4) Delay for 10 milliseconds. 5) Write xxxx x010 to the PPROG register to turn off the programming voltage. 6) Repeat steps 2 through 5 until all desired locations have been programmed. 7) Write EELAT bit back to zero to allow the programmed data to be verified. ERASE - If the E clock frequency is less than 1 MHz, the CSEL bit in the OPTION register must be set when erasing the EEPROM. Three erase modes of EEPROM: 1) full 512-byte simultaneous "bulk" erase 2) "row" erase where only one row (16 bytes) is erased at a time and 3) "byte" erase where a single specified byte is erased. NOTE The erased state of all EEPROM cell is logic one. On early parts, byte and row erase are not implemented. Normal procedures for erasure of the entire EEPROM: 1) Write xxxx 0110 to the PPROG register. This specifies the "all" erase mode (ROW bit=0), erase mode (ERASE bit=1), EEPROM configured for address/data latching (EELAT bit=1), and erase voltage turned off (EEPGM bit=0). 1a) A write must be done to any EEPROM address after Step 1. 1b) Optionally, if the CONFIG register is also to be erased, a write to the address ofthe CONFIG register must be performed after "bulk" erase was specified by the write, in step 1 above, and before programming volt- age is turned on in step 2 below. In the case of erasure, the data involved in this write operation is unimportant and the write is needed only for the addressing information it provides. 2) Write xxxx 0111 to the PPROG register toturn on the the erase voltage to the EEPROM array. 3) Wait for 10 milliseconds to allow the erasure to com- plete. 33 4) Write xxxx 0110 to the PPROG register to turn off the erase voltage. 5) Write xxxx 0000 to the PPROG register to return the EEPROM to the normal read configuration. Normal procedure for erasure of a row of EEPROM: 1) Write xxxx 1110 to the PPROG register. This specifies the "row" erase mode (ROW bit=1), erase mode (ERASE bit=1), address/data buses configured to latch row address informa- tion (EELAT bit =1), and erase voltage turned of (EEPGM=0). 2) Write to an address in the EEPROM row to be erased (each row is 16 bytes). This latches the row addressing informa- tion for the row to be erased. 3) Write xxxx 1111 to the PPROG register to turn on the erase voltage to the EEPROM array. 4) Wait for 10 milliseconds to allow the erasure to com- plete. 5) Write xxxx 1110 to the PPROG register to turn off the erase voltage. 6) Write xxxx 0000 to the PPROG register to return the EEPROM to the normal read configuration. Normal procedure for erasure of a single byte of EEPROM: 1) Write xxx1 x110 to the PPROG register. This specifies the byte erase mode (BYTE=1; ROW=x), erase mode (ERASE bit=1), address/data buses configured to latch address information (EELAT bit=1), and erase voltage turned off (EEPGM bit=0). 2) Write to the address in the EEPROM to be erased (data is ignored). This latches the address of the byte to be erased. 3) Write xxx1 x111 to the PPROG register. This turns on the erase voltage to the EEPROM array. EEPGM was not changed to one in the same write operation as the write that configured ROW, ERASE, and EELAT because of the possibility of enabling the erase voltage before the erase mode specification was stable. 4) Wait for 10 milliseconds to allow the erasure to com- plete. 34 5) Write xxx1 x110 to the PPROG register to turn off the erasure voltage. 6) Write xxx 0000 to the PPROG register to return the EEPROM to the normal read configuration. The COPRST Register is used to reset the watch dog timer. The se- quence required to accomplish this is : 1) write $55 to the CORPST register at $B03A, followed by 2) write $AA to the same address. Both writes must occur in correct order prior to timeout but,any number of instructions may be executed between the writes. The elapsed time between adjacent software reset sequences must never be greater than the COP timeout period. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |Bit 7|Bit 6|Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0| $B03A COPRST |-----|-----|-----|-----|-----|-----|-----|-----| The HPRIO register is used to select one of the I bit related in- terrupt sources to be elevated to the highest I bit masked posi- tion in the priority resolution circuit. In addition, four mis- cellaneous system control bits are included in this register. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| |RBOOT| SMOD| MDA | IRV |PSEL3|PSEL2|PSEL1|PSEL0| $B03C HPRIO |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7 RBOOT The read bootstrap ROM bit only has meaning when the SMOD bit is a logic one (special bootstrap mode or special test mode). At all times, this bit reverts to its logic zero disabled state and may not be written. When set, upon reset in bootstrap mode only, the small bootstrap loader program is enabled. When clear, by reset in the other three modes, this ROM is disabled and accesses to this area are treated as external accesses. Bit 6 SMOD The special mode write-only bit reflects the status of the MODB input pin at the rising edge of reset. It is set if the MODB pin is at or above 1.8 times VDD volts during reset. Otherwise, it is cleared or under software control from the special modes. 35 Bit 5 MDA The mode select A bit reflects the status of the MODA input pin at the rising edge of reset. While the SMOD bit is a logic one (special test or special bootstrap mode in effect), the MDA bit may be written, thus, changing the operating mode of the MCU. When the SMOD bit is a logic zero, the MODA bit is a read-only bit and the operating mode cannot be changed without going through a reset sequence. The table below summarizes the relationship between the SMOD and MDA bits and the MODB and MODA input pins at the rising edge of reset. |-------------|-------------------------------|------------| | | | Latched at | | Inputs | | Reset | | | Mode Description | | |------|------| |------|-----| | MODA | MODB | | SMOD | MDA | |------|------|-------------------------------|------|-----| | 0 | 1 | Single Chip (Mode 0) | 0 | 0 | | 1 | 1 | Expanded Multiplexed (Mode 1) | 0 | 1 | |------|------|-------------------------------|------|-----| | 0 | * | Special Bootstrap | 1 | 0 | | 1 | * | Special Test | 1 | 1 | |------|------|-------------------------------|------|-----| 1 = logic high 0 = logic low * = 1.8 * = 1.8 times VDD(or higher) Bit 4 IRV The internal read visibility bit is used in the spe- cial modes (SMOD=1) to affect visibility of internal reads on the expansion data bus. IRV is writable only if SMOD=1 and returns to zero of SMOD=0. If the bit is zero, visibility of internal reads are blocked. If the bit is one, internal reads are visible on the external bus. Bit 3-0 PSEL3,PSEL2,PSEL1,PSEL0 These four select bits are used to specify one I bit related interrupt source which becomes the highest priority I bit related source. |-----|-----|-----|-----|------------------------------------| |PSEL3|PSEL2|PSEL1|PSEL0| Interrupt Source Promoted | |-----|-----|-----|-----|------------------------------------| | 0 | 0 | 0 | 0 | Timer Overflow | | 0 | 0 | 0 | 1 | Pulse Accumulator Overflow | | 0 | 0 | 1 | 0 | Pulse Accumulator Input Edge | | 0 | 0 | 1 | 1 | SPI Serial Transfer Complete | |-----|-----|-----|-----|------------------------------------| | 0 | 1 | 0 | 0 | SCI Serial System | 36 | 0 | 1 | 0 | 1 | Reserved (Default to IRQ) | | 0 | 1 | 1 | 0 | IRQ (External Pin or Parallel I/O) | | 0 | 1 | 1 | 1 | Real Time Interrupt | |-----|-----|-----|-----|------------------------------------| | 1 | 0 | 0 | 0 | Timer Input Capture 1 | | 1 | 0 | 0 | 1 | Timer Input Capture 2 | | 1 | 0 | 1 | 0 | Timer Input Capture 3 | | 1 | 0 | 1 | 1 | Timer Output Compare 1 | |-----|-----|-----|-----|------------------------------------| | 1 | 1 | 0 | 0 | Timer Output Compare 2 | | 1 | 1 | 0 | 1 | Timer Output Compare 3 | | 1 | 1 | 1 | 0 | Timer Output Compare 4 | | 1 | 1 | 1 | 1 | Timer Output Compare 5 | |-----|-----|-----|-----|------------------------------------| Note: During reset, PSEL3, PSEL2, PSEL1 and PSEL0 are initialized to 0:1:0:1 which corresponds to "Reserved (default to IRQ)" being the highest priority I bit related interrupt source. Interrupts in the 68HC11 obey a fixed hardware priority circuit to resolve simultaneous requests; however, one I bit related in- terrupt source may be elevated to the highest I bit priority posi- tion in the resolution circuit. The first six interrupt sources are not masked by the I bit in the condition code register and have the fixed priority interrupt relatioship of: reset, clock monitor fail, COP fail, illegal opcode and XIRQ. (SWI is actually an instruction and has highest priority other than reset in the sense that once the SWI opcode is fetched no other interrupt can be honored until the SWI vector has been fetched). Each of these sources is an input to the priority resolution circuit. The highest I bit masked priority input to the resolution circuit is assigned under software control (of the HPRIO register) to be con- nected to any one of the remaining I bit related interrupt sources. In order to avoid timing races, the HPRIO register may only be written while the I bit related interrupts are inhibited (I bit in condition code register is a logic one). An interrupt that is assigned to this high priority position is still subject to masking by any associated control bits or the I bit in the con- dition code register. The interrupt vector address is not af- fected by assigning a source to this higher priority position. The INIT Register is special purpose 8-bit register is used (optionally) during initialization to change the default loca- tions of RAM and internal registers in the MCU memory map. It may be written to only once within the initial 64 E cycles after a reset and thereafter becomes a read-only register. B7 B6 85 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | RAM3| RAM2| RAM1| RAM0| REG3| REG2| REG1| REG0| $B03D INIT |-----|-----|-----|-----|-----|-----|-----|-----| 37 The default starting address for internal RAM is $0000 and the default starting address of the 64 byte internal register space is $1000 (the INIT register is initialized to $01 by reset). The upper four bits of the INIT register specify the starting address for the internal 256 byte RAM and the lower four bits of INIT specify the starting address for the 64 byte internal register space. The four bits reflect the upper nibble od the 16-bit ad- dress. The Max-FORTH operating system moves the registers to $B000 at reset for all versions with Revision 2 ($9000 for Rev 0 - 1). The TEST1 Register at $B03E is only available in the test mode, so is not included in this section. The 68HC11 allows an end user to configure the MCU system to his specific requirements through the use of hardwired options such as the mode select pins, semi-permanent EEPROM control bit specification. The CONFIG control register is implemented in EEPROM cells and controls the presence of ROM and EEPROM in the memory map, as well as the COPON COP watchdog system enable. An optional security feature is available intended to allow user protection of data in 68HC11 EEPROM and RAM. B7 B6 B5 B4 B3 B2 B1 B0 |-----|-----|-----|-----|-----|-----|-----|-----| | - | - | - | - |NOSEC|NOCOP|ROMON| EEON| $B03F CONFIG |-----|-----|-----|-----|-----|-----|-----|-----| Bit 7-4 Not implemented. Read as logic zero. Bit 3 NOSEC Security Mode Option Bit. When the security mask option is specified, this bit can be used to enable a software antitheft mechanism. When cleared, this bit forces the MDA mode control bit to zero so that only single-chip modes of operation can be selected. If the bit is cleared when the MCU is reset in the special bootstrap mode, EEPROM and RAM are erased before the boot loading process con- tinues. Bit 2 NOCOP COP System OFF. When this bit is clear, the COP watchdog forced reset function is enabled. When this bit is set, the COP watchdog circuit is disabled. Bit 1 ROMON Enable On-Chip ROM Select Bit. When this bit is clear, the 8K internal ROM is disabled and that memory space becomes externally accessed space. Bit 0 EEON Enable On-Chip EEPROM Select Bit. When this bit is clear, the 512-byte internal EEROM is disabled and that memory space becomes externally accessed space. 38 Since the CONFIG register is implemented with EEPROM cells, spe- cial provisions must be made to erase and program this register. The normal EEPROM control bits in the PPROG register are used for this purpose. 39